1. Field of the Invention
This invention relates to a semiconductor logical circuit, and more particularly to a semiconductor encoder apparatus logical circuit which retrieves a bit holding a first logical "1" from the high order or the low order of data of, for example, 32-bit size, thereby encoding at high speed the retrieved result to produce an output offset value of, for example, binary digit 5-bit.
2. Description of the Prior Art
A conventional microprocessor includes a semiconductor logic circuit (e.g., encoder) for encoding data of, for example, 32-bit size, by eliminating an input offset value.
FIG. 1 is a flow chart showing the operation of a conventional encoding apparatus, and FIG. 2 is a schematic block diagram thereof.
At first, explanation will be given on encoding the data of 32-bit size. The data of 32-bit size is outputted from a data bus 1 and given to a barrel shifter 22. The barrel shifter 22 logically shifts the data of 32-bit size rightwardly to an extent of input offset value, thereby omitting a part to be masked. Next, the barrel shifter 22 now logically shifts the rightwardly shifted data leftwardly to an extent of input offset value. Therefore, the masked portions entirely become logical "0". Thus, the data omitting therefrom the masked portions is given to an encoder 21 through the data bus 1 and encoded therewith, so that a logical "1" is retrieved from the input offset value with respect to the high order data.
In the aforesaid conventional semiconductor logical circuit, masking of data of 32-bit size is carried out by use of the barrel shifter 22, whereby it takes three steps to carry out encoding (refer to FIG. 1), thereby creating a problem in that the processing speed becomes slow.